When connecting circuits having different power source voltages, the level of an output signal of one circuit should be shifted to the level of the other circuit receiving the output signal. In general, a level shifter accomplishes this task. As seen in FIGS. 1A and 1B, a conventional level shifter typically includes inverters and four transistors MN11, MN12, MP11, and MP12. The transistors MP11 and MP12 are p-channel MOS (PMOS) transistors, and the transistors MN11 and MN12 are n-channel MOS (NMOS) transistors. Level shifters may be characterized based on the interconnection of the transistors as either a latch-type level shifter (FIG. 1A) or a mirror-type level shifter (FIG. 1B).
Because of the cross coupled structure of the transistors MP11 and MP12, there is no static current (i.e. a current through the transistors MP11 or MP12 when the output of the level shifter is in a steady state) in the latch-type level shifter illustrated in FIG. 1A. In particular, when the transistor MN11 is on and the transistor MN12 is off, the gate of the transistor MP12 is pulled low and the transistor MP12 is on, which pulls the gate of the transistor MP11 high and turns off the transistor MP11. When the transistor MN11 is off and the transistor MN12 is on, the gate of the transistor MP11 is pulled low and the transistor MP11 is on, which pulls the gate of the transistor MP12 high and turns off the transistor MP12. Thus, a current path is not formed through either transistors MP11 and MN11 or MP12 and MN12.
However, the performance of the latch-type level shifter is strongly affected by the voltage of vdd2, since the gate-to-source voltage of PMOS transistors MP11 and MP12 is the voltage vdd2, whereas the gate-to-source voltage of NMOS transistors MN11 and MN12 is the voltage vdd1. Thus, the range of voltages of vdd2 over which a latch-type level shifter may function properly may be narrow.
A mirror-type level shifter is illustrated in FIG. 1B. As seen in FIG. 1B, the gates of the PMOS transistors MP11 and MP12 are coupled together and to the drain of the transistor MP11. Because the performance is determined by the current of the transistors MP11 and MN11, even if the output voltage vdd2 is changed, there will typically be no severe performance change in the level shifter. Thus, it may be possible to use the mirror-type level shifter for various output voltage circuits. However, when MN11 is on, the gates of the transistors MP11 and MP12 are pulled low and the transistors MP11 and MP12 are on. Thus, a static current path is formed through the transistors MP11 and MN11.
A further difficulty in providing level shifter circuits is that the core supply voltage (vdd1) used in, for example, ultra deep submicron CMOS technologies, is reduced, while the I/O section supply voltage (vdd2) is kept at a high level. As the core supply voltage vdd1 is reduced, the gate-source voltage driving the NMOS transistor NM11, NM12 is also reduced. Thus, the driving capability may be reduced to a point where the level shifter does not provide reliable operation.
For example, as the core voltage (vdd1) decreases and the difference of vdd1 and threshold voltage (Vthn) of the NMOS transistors is lowered to nearly zero, the level shifter may not provide reliable operation. In particular, the current (IMN12) of the transistor MN12 is provided by the following equation:
      I    MN12    =                              μ          N                ⁢                  C          OX                    2        ⁢                  (                  W          L                )            MN12        ⁢                  (                  vdd1          -                      V            thn                          )            2      where W and L are the gate width and length, COX is the oxide capacitance and μN is the surface electron mobility. As is seen from the above equation, as the difference between vdd1 and the threshold voltage Vthn approaches zero, the current through the transistor also approaches zero. To overcome this limitation, the difference between vdd1 and the threshold voltage Vthn may be increased by decreasing the threshold voltage Vthn. However, to reduce the threshold voltage, the transistors typically utilize thin oxides and shallow implants. Such a thin oxide transistor may be more susceptible to voltage stress when operated in conjunction with the higher voltage vdd2.
FIG. 2 is a circuit diagram of a level shifter such as described in Japanese Patent Application No. JP7086913. As seen in FIG. 2, a delay element provided by the inverters INV1 and INV2 and a transistor MP13 is provided in addition to a conventional current-mirror level shifter circuit. The transistor MP13 is placed in series with the transistors MP11 and MN11 and is controlled by the output of the delay element. The feedback signal from Y is used to control the transistor MP13 to block the static current when A is high.
FIG. 3 is a schematic diagram of a level shifter circuit as described in U.S. Pat. No. 6,556,061. As seen in FIG. 3, zero threshold transistors MN31 and MN32 have been incorporated in a conventional latch-type level shifter. The gates of the transistors MN31 and MN32 are tied to vdd1 (the lower voltage supply). The transistors MN11 and MN12 are thin oxide transistors that have a lower threshold voltage. Because the gate voltage of MN31 and MN32 is vdd1 and the threshold voltage of MN31 and MN32 is zero, the maximum drain voltage of MN11 and MN12 is vdd1 i.e. Vg−Vthn=Vdd1−0). Therefore, it is possible to use low threshold voltage transistors for MN11 and MN12.